This invention relates to a semiconductor memory device and a data readout method therefor and more particularly to a fast cycle synchronous DRAM (SDR-FCRAM) having a function of rapidly reading/writing random data from or into a memory cell array in synchronism with a clock signal and a data readout method for a double data rate synchronous DRAM (DDR-FCRAM) for realizing the data transfer rate twice that of the above DRAM.
In order to enhance the data access speed of a DRAM to that of an SDRAM and attain a large data band width (the number of data bytes for each unit time) by use of a high clock frequency (cycle time tCK), a synchronous DRAM (SDRAM) is invented and is already put into practice from the 4-Mbit or 16-Mbit DRAM generation.
Recently, in order to further enhance the operation speed of the SDRAM, a double data rate SDRAM which is operated at the data transfer rate twice that of the conventional SDRAM by operating the same in synchronism with both of the rise edge and fall edge of a clock signal is proposed and actively commercialized.
In order to enhance the data transfer rate, the data bandwidth is actively increased, but it is difficult to enhance the speed of random access to cell data in a memory core, that is, the sped of data access to a row address which has been changed to indicate a different row. This is because the cycle time (random cycle time=tRC) of the memory core cannot be greatly reduced since a certain period of time (which is referred to as core latency) is required for the destructive readout and amplifying operation inherent to the DRAM and the precharge operation prior to the next access to the memory core.
In order to solve the above problem, a so-called fast cycle RAM (FCRAM) in which access to the memory core and the precharge operation thereof are pipelined to reduce the random cycle time to half of that of the conventional DRAM or less is proposed and will be started to be commercialized mainly in the network field in which random data of a router or LAN switch using SRAMs in the prior art is transferred at high speed.
The basic system of the data readout operation of the FCRAM is described in International Application (International Publication Number W098/56004 (Fujioka et al.)) based on Jpn. Pat. Appln. Nos. H09-145406, H09-215047 and H09-332739 used as the basic application, for example.
This invention is to improve the data readout operation of the FCRAM defined in the above International Application and relates to the improvement of a method for supplying a row access instruction and column access instruction.
First, the basic system and the operation of data readout in the FCRAM disclosed in the above International Application are briefly explained with reference to FIGS. 1 to 5. FIGS. 1 to 3 correspond to FIGS. 4 to 6 in International Publication No. W098/56004.
FIG. 1 is a principle diagram for reducing or shortening the random cycle time tRC in the FCRAM and shows a row-series pipeline operation. FIG. 2 is a detail timing chart of an internal operation for realizing the pipeline operation. FIG. 3 is a timing chart for illustrating the operation for enhancing the row access speed by the self-precharge operation. FIG. 4 shows an example of a command input method at the readout time defined in the FCRAM. FIG. 5 is a command status diagram in the data readout system described in the above International Application.
In FIGS. 2 and 3, WL indicates the potential of a word line, BL, {overscore (BL)} indicate the potentials of paired bit lines, SAE indicates an enable signal of a bit line sense amplifier, CSL indicates a signal (which is the potential of the column selection line) selected according to a column address, for transferring data on the bit line pair BL, {overscore (BL)} amplified by the bit line sense amplifier to a peripheral data bus, EQL is a precharge/equalizing signal for the paired bit lines, ACT indicates a row access command and RD is a column access command.
In FIG. 4, BA0 to BA3 indicate a bank address, A0 to A10 indicate an address, UA indicates an upper address, LA0 to LA9 indicate a lower address, and LA1, LA0 among the lower address LA0 to LA9 indicate a burst address.
In FIG. 5, DESL indicates a deselect operation, POWER DOWN indicates a power down operation, MODE REGISTER indicates a mode register, WRITE indicates a write operation, IDLE indicates a 50% adder latched, READ indicates a read operation, AUTO-REFRESH indicates an auto-refresh operation, SELF-REFRESH indicates a self-refresh operation, PDEN indicates a power down command, PDEX indicates a power down release command, MRS indicates a mode register set command, ACT indicates a row access command (first command), RD indicates a read column access command (second command), REF indicates a auto refresh command, WR indicates a write access command, SELF indicates a self-refresh command and SELFX indicates a self-refresh release command.
In order to enhance the speed of random data readout from a memory cell array, it is considered that the following three stages are pipelined as shown in FIG. 1:
(1) command decoding operation and peripheral circuit operation;
(2) sense amplification operation; and
(3) data output operation.
In this case, in the DRAM, the longest time is required for the stage (2), that is, for xe2x80x9cword line selection cyclexe2x80x9d+xe2x80x9csense amplifier driving cyclexe2x80x9d+xe2x80x9creset cycle (sense amplification cycle)xe2x80x9d as shown in the timing chart of FIG. 2. In order to reduce the time to minimum, instead of decoding the row address, subjecting data read out from the memory cell MC connected to the selected word line WL to the differential amplification by the bit line sense amplifier S/A, terminating the restore operation, and then successively opening the column selection gates in response to a plurality of column addresses by use of the column selection lines CSL to make burst access as in the conventional SDRAM, it is necessary to read out data of a necessary burst length to the bit line sense amplifier S/A so as to instantly terminate the sense amplifying operation (stage (2)) by simultaneously opening a plurality of column selection gates larger in number than the SDRAMs after the restore operation is terminated and then effect the reset (precharge) cycle in the shortest time while the data outputting operation (stage (3)) is being effected.
In order to realize the above operation, the operation based on the timing chart shown in FIG. 3 is required. The feature of the operation shown in FIG. 3 is that a row access command ATC and column access command RD (in this case, it indicates xe2x80x9creadxe2x80x9d) are supplied to the FCRAM as one packet. The commands are supplied in response to successive clock input pulses so that the command interval will become minimum and the command cycle time can be reduced. By fetching the row access command ACT and column access command RD in synchronism with the two successive clocks, it becomes possible to fetch a column address CAi which is fetched at the same time as the column access command RD at earlier timing, thereby making it possible to select a column selection line CSL at earlier timing. Further, as a secondary effect, part of the column address CAi can be used as an address for dividing the sense amplifiers, and therefore, the number of sense amplifiers to be operated is limited in comparison with the conventional DRAM and the operation speed of the stage (2) can be enhanced.
AS shown in FIG. 5, in the above readout method, a row address is latched in response to input of a first command ACT in the deselect state (standby state) to start the operation of the row-series peripheral circuit. Next, part of the column address CAi is used as a row address for decoding the sense amplifier by use of the second command RD (column access command for xe2x80x9creadxe2x80x9d) or {overscore (WR)} (column access command for xe2x80x9cwritexe2x80x9d) and access to the thus limited memory core is started. Then, after termination of the access, the deselect state is automatically restored.
However, the above command system has the following problem. That is, since the row access command is supplied only for decoding the command and starting the operation of the peripheral circuit, the operations of the stages (2) and (3) cannot be started until a column access command RD (xe2x80x9creadxe2x80x9d in this case) is input one cycle after the present cycle. Therefore, the random cycle time tRC is defined by an interval between the row access commands ACT and ACT or between the column access commands RD and RD and can be reduced without causing any problem, but data access from the row access command ACT, that is, random access time tRAC will contain an extra one clock cycle.
In order to cope with this, in the above International Application, a system for simultaneously inputting the row access command ACT and column access command RD is proposed. However, in this system, since the command decoding operation is extremely complicated and the logic construction of the internal circuit becomes larger, there occurs a possibility that extra delay time occurs in the front half part of the random access time tRAC. Further, since the command decoding operation becomes complicated, the number of input pins of the device may be increased in many cases and there occurs a possibility that the package size will be increased and the cost will rise.
As described above, in the conventional semiconductor memory device, if the row access command and column access command are given as one packet in order to enhance the speed of random data readout from the memory cell array, data access from the row access command, that is, the random access time will contain an extra one clock cycle without fail.
In order to solve this problem, a system for simultaneously inputting the row access command and column access command is proposed, but in this case, since the command decoding operation is extremely complicated and the logic construction of the internal circuit becomes larger, there occurs a possibility that extra delay time occurs in the front half part of the random access time. Further, there occurs a possibility that the package size will be increased and the cost will rise due to an increase in the number of input pins of the device.
According to an aspect of the present invention, there is provided a semiconductor memory device in which first and second commands are input to effect a read/write operation of random data with respect to a memory cell array in synchronism with a clock signal and a row access command and a column access command for data readout are supplied as one packet in two successive clock cycles, comprising: a first pin supplied with a signal which distinguishes a read command and a write command; second pins supplied with upper-side and lower-side decode addresses; a controller to which a signal indicating that the read command is input and a signal indicating that the write command is input based on the signal input to the first pin are supplied; a first command decoder controlled by an output signal of the controller, which defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via the second pin and decoding the first command; and a lower-side command decoder controlled by an output signal of the controller, which fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command and outputs a lower address latch command, mode register set command and auto-refresh command.